The present invention relates to a memory tester for testing memories formed, for example, by semiconductor integrated circuits and, more particularly, to a pattern generating method for use in testing memories of the type that respond to a start address to generate burst addresses and hence permits fast write and read. The invention pertains as well to a pattern generator using the pattern generating method, and a memory tester using the pattern generator.
FIG. 6 illustrates in block form the general configuration of an IC tester. Reference character TES denotes generally the IC tester. The IC tester TES comprises a main controller 111, a pattern generator 112, a timing generator 113, a waveform formatter 114, a logic comparator 115, a driver 116, an analog comparator 117, a failure analysis memory 118, a logical amplitude reference voltage source 121, a comparison reference voltage source 122 and a device power source 123.
The main controller 111 is formed, in general, by a computer system and operates under the control of a test program prepared by a user, controlling the pattern generator 112 and the timing generator 113. The pattern generator 112 generates test pattern data DT, which is converted by the waveform formatter 114 to a test pattern signal of a waveform that meets specifications of a memory under test 119. The test pattern signal is provided to the driver 116 wherein It is voltage-amplified to a waveform having an amplitude value set in the logical amplitude reference voltage source 121. The test pattern signal thus voltage-amplified is then applied to the memory under test 119 for storage therein.
A response signal read out of the memory under test 119 is compared by the analog comparator 117 with a reference voltage fed from the reference voltage source 122 to decide whether the response signal has a predetermined logic level (voltage of a logic xe2x80x9cHxe2x80x9d or xe2x80x9cLxe2x80x9d). The response signal decided to be at the predetermined logic level is compared by the logic comparator 115 with expectation data EXP provided from the pattern generator 112. If a mismatch is found between the response signal and the expectation data EXP, it is decided that memory cell of the address from which the response signal was read out is failing, and upon each occurrence of such a failure, the faulty address is stored in the failure analysis memory 118 for use in deciding, after completion of the test, whether the failed cell is repairable.
FIG. 7 which is drafted by the present inventor, illustrates in block form the internal configuration of the pattern generator 112 which employs, for example, the expectation data generating method disclosed in Japanese Patent Application Laid-Open Gazette 08-036035 (Laid Open Feb. 6, 1996). The pattern generator 112 comprises: a program memory 11 in which there are stored microprograms for pattern generation use; a read address generating part 12 which determines an address for reading out the program memory 11; an address data generating part 13 which generates address data for input to the memory under test 119; a mask data generating part 15 which generates mask data MD for bitwise masking of test pattern data to be written into the memory under test 119; a pattern data generating part 15 which generates pattern data TP; an expectation data generating part 16 which generates from the pattern data TP and the mask data MD the expectation data EXP to be supplied to the logic comparator 115; and a multiplexer 17 which selects and outputs one of the pattern data TP from the pattern data generating part 15 and the expectation data EXP from the expectation data generating part 16.
Incidentally, the output from the multiplexer 17 will be identified by DT in the FIG. 7 example and the following description. Accordingly, DT is the pattern data DT at the write timing of the memory under test 119 and the expectation data EXP at the read timing.
The read address generating part 12 is composed of a program counter PC and a arithmetic logic unit ALU. The read address of the program memory 11 indicated by the program counter PC is subjected to an arithmetic operation, such as an addition or subtraction, based on an operation control instruction PC-C containing an operation value and written in the microprogram which is read out of the program memory 11 for the next test cycle, and the operation result is used to update the value of the program counter PC.
The address data generating part 13, the mask data generating part 14 and the pattern data generating part 15are each composed of an arithmetic logic unit ALU and a register RG. The values indicated by the registers RG, from which they are output as the address data XB, the mask data MD and the pattern data TP, respectively, are subjected to an arithmetic operation, such as an addition or subtraction, based on operation control instructions XB-C, MD-C and TP-C containing operation values and written in the microprograms which are read out of the program memory 11 for the next test cycle, and the operation results are used to update the values of the registers RG.
The address data XB and the pattern data TP are each converted by the waveform formatter 114 to a signal of a waveform that meets the specifications of the memory under test 119. Read/write control instruction R/W for the memory under test 119 is read out directly from the program memory 11, and is similarly converted by the waveform formatter 114 to a signal of a waveform that fulfills the specification of the memory under test 119, thereafter being input thereto.
Now, a description will be given of the mask data MD that is generated in the mask data generating part 14. Some memory devices have a bit-wise masked write function that inhibits a write for each bit of write data. In the testing of such a memory, the expectation data generating part 16 is required to generate expectation data EXP that has, at bit positions currently masked with the mask data MD, the same bit data as that written previously but has currently written bit data at currently unmasked bit positions.
The expectation data generating part 16 is specifically designed to satisfy the required with ease. That is, the expectation data generating part 16 is made up of a logic inverter INV and an exclusive OR circuit EOR. The mask data MD is provided via the logic inverter INV to the one input terminal of the exclusive OR circuit EOR, and the pattern data TP from the pattern data generating part 15 is fed to the other input terminal of exclusive OR circuit EOR. The exclusive OR circuit EOR outputs exclusive ORs of corresponding bits of the two pieces of input data.
In the case of effecting a write in the memory under test 119 while masking with the mask data MD and reading out the results of the data written from the memory 119, the multiplexer 17 selects and outputs expectation data EXP generated in the expectation data generating part 16 by the inversion of a control signal EXP-S to, for example, a logic xe2x80x9c1xe2x80x9d. This expectation data EXP is provided to the logic comparator 115.
In the mask data MD the mask bit (a write inhibit bit) has a logic xe2x80x9c0xe2x80x9d and the non-mask bit (a write enable bit) has a logic xe2x80x9c1xe2x80x9d. Those bits of the mask data MD given the logic xe2x80x9c0xe2x80x9d are each inverted to xe2x80x9c1xe2x80x9d by the inverter INV in the expectation data generating part 16, and function as a signal for logic inversion of the corresponding bit in the pattern data TP. On the other hand, those bits given the logic xe2x80x9c1xe2x80x9d are each inverted to xe2x80x9c0xe2x80x9d by the inverter INV in the expectation data generating part 16, allowing the corresponding bit in the pattern data TP to be output intact at the logical level of its own. That is, in the expectation data generating part 16 the pattern data TP undergoes logic inversion at the bit positions corresponding to the mask bits of the mask data MD, thereafter being provided as the expectation data EXP.
In the case of writing xe2x80x9c0sxe2x80x9d in all bits (memory cells) of the memory under test 119 for initialization and then effecting a write therein by applying pattern data with all bits at the logic xe2x80x9c1xe2x80x9d level while masking alternate bits (alternate memory cells), the logic xe2x80x9c1sxe2x80x9d ought to be written in the memory cells of each address of the memory 119 corresponding to the unmasked bits, and the logic xe2x80x9c0sxe2x80x9d ought to be written in the memory cells corresponding to the masked bits. Accordingly, by inputting to the expectation data generating part 16 the pattern data TP with all bits at the logic level xe2x80x9c1xe2x80x9d and the mask data MD used for bit-wise masking, it is possible to obtain the same data as that which ought to have been written as the expectation data EXP in the memory 119; hence, the expectation data generating part 16 can generate correct expectation data EXP.
FIG. 8 shows how the expectation data EXP is generated as described above. Incidentally, FIGS. 8 to 14 are tables prepared by the inventor of this application for explaining the write/read operation in the memory under test. Column A in FIG. 8 depicts how to effect the write in the memory under test for initialization. This example shows the case where, at a write address #0, all xe2x80x9c1sxe2x80x9d mask data which enables a write in all bits are provided and all xe2x80x9c0sxe2x80x9d pattern data TP is written.
Column B shows the state in which a write has been effected in the address #0 with alternate bits masked (hereinafter referred to as bit-wise masking). The mask data MD is data xe2x80x9c10101010 . . . xe2x80x9d with xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d alternating with each other. The pattern data TP is inverted to all xe2x80x9c1sxe2x80x9d, and the inverted data is selected by the multiplexer 17 and written as the signal DT in the memory under test.
In the memory under test there is written the logic xe2x80x9c1xe2x80x9d in each memory cell corresponding to a bit of logic xe2x80x9c1xe2x80x9d in the mask data MD and there is stored the initially written logic xe2x80x9c0xe2x80x9d in each memory cell corresponding to the logic xe2x80x9c0xe2x80x9d of the mask data MD because the write therein is inhibited.
Column C in FIG. 8 shows the case where data RD, read out of the memory under test after effecting a write therein while masking, matches the expectation data EXP.
At the time of reading the memory, the mask data MD used for the write and the pattern data TP are fed to the expectation data generating part 16, generating expectation data EXP (eighth cell in column C of the FIG. 8 table). The mask data MD is, in this example, data in which xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d alternate with each other, and the pattern data TP is all xe2x80x9c1sxe2x80x9d data. Accordingly, the expectation data EXP, which is provided from the expectation data generating part 16 and selected by and output from the multiplexer 17, is data in which xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d alternate with each other as is the case with the mask data MD. This expectation data EXP matches data RD (the lowest cell in column C of the FIG. 8 table) that is read out of the memory under test, from which it will be understood that the expectation data can be generated correctly.
Incidentally, xe2x80x9cInvalidxe2x80x9d in FIG. 8 represents data that is not used. That is, it indicates that the mask data MD is not ever used in the readout of the memory under test in the FIG. 8 example. The same is true of FIGS. 11 and 13 as well.
The above is a method for generating the expectation data for the memory whose addresses have a one-to-one correspondence with externally accessed addresses. With the recent development of high-capacity, fast write/read memories, there has been proposed a burst-type memory wherein an externally input address is used as a start address to generate burst addresses which access specifically defined memory spaces one after another and external data is written in the burst address spaces and read out thereform. Some burst-type memories are of such one in which each address has memory cells constituting plural bytes each composed of eight or nine bits and that possesses, unlike in the afore-mentioned memory, a function by which a write in all memory cells (consisting of plural bytes) of each burst address is controlled on a byte-wise basis with the corresponding bits of the input mask data (hereinafter referred to as byte-wise masked write function). Accordingly, one-bit mask data is used for each byte; for instance, in the burst-type memory described below which has memory cells of two bytes for each address, a write in the memory cells of two bytes is controlled using the mask data of two bits.
Turning next to FIG. 9, a description will be given of the general operation and the byte-wise masking function of a Direct Rambus DRAM that is one of the burst type memories. FIG. 9A depicts a clock signal CLOCK which is applied to the Direct Rambus DRAM; FIG. 9B depicts control pins COL0 to COL4 for inputting therethrough a start address signal, control signals for controlling write and read operations, mask data and so forth; and FIGS. 9C and 9D depicts data I/O pins DQA0 to DQA8 and DQB0 to DQB8 for inputting and outputting therethrough write data signals and readout data signals, respectively.
The control pins COL0 to COL4 are supplied with a control packet COLC for inputting control instructions, start addresses and so forth and a mask packet COLM for inputting mask data. The control packet COLC is input to the pins COL0 to COL4 as parallel data of a 5-bit width in this example, and if a signal that is applied to a predetermined one of the pins, for example, COL0, is S=1, the Direct Rambus DRAM recognizes that the data to be input to the pins COL0 to COL4 is the packet COLC for inputting a start address. The read and write operations are specified by control signals COP0 to COP3 contained in the packet COLC. The start address at this time is specified by control signals C0 to C5. Other control signals are required for device recognition and for bank specification, for instance, but since they are not particularly related to the present invention, no description will be given of them.
In the case of the mask packet COLM that is input to the pins COL0 to COL4, if the signal to be applied to, for example, the pin COL1 is M=1, the Direct Rambus DRAM recognizes that the input data is a packet for inputting mask data. The mask packet COLM contains twp pieces of mask data MA0 to MA7 and MB0 to MB7; two bits of two pieces of mask data MAn and MBn (where n=0, 1, . . . , 7) of each corresponding number represent mask data for controlling a two-byte write in each address.
The data I/O pins DQA0 to DQA8 and DQB0 to DQB8 are shown to be supplied with two pieces of parallel data DQA and DQB. The two pieces of parallel pattern data DQA and DQB are written in burst addresses #0 to #7 which are generated in the memory. In this example, data of eight addresses is input.
WA00 to WA80 and WB00 to WB80 forming the two pieces of parallel pattern data DQA and DQB are each parallel pattern data of one byte consisting of nine bits. The two pieces of parallel pattern data are arranged in time sequence and input as a sequence of parallel pattern data to the memory.
FIG. 10 shows the relationships between the burst addresses #0 to #7 and mask data MA0 to MA7, MB0 to MB7 and parallel pattern data that is written in each of the burst addresses #0 to #7. Depending on whether the two pieces of mask data MA0 and MB0 assigned to the burst address #0 are logic xe2x80x9c1sxe2x80x9d or xe2x80x9c0sxe2x80x9d, it is decided whether the pieces of parallel pattern data WA00 to WA80 and WB00 to WB80 to be written in the burst address #0 are masked on a byte-wise basis.
That is, if the mask data MA0 is a logic xe2x80x9c1xe2x80x9d, the parallel pattern data WA00 to WA80 is write-enabled, and if the mask data MB0 is a logic xe2x80x9c0xe2x80x9d, the parallel pattern data WB00 to WB80 is write-inhibited. For the other burst addresses #1 to #7, too, the masking operation is similarly controlled, depending on the logical values of the mask data MA1 to MA7 and MB1 to MB7.
As described above, in the Direct Rambus DRAM the burst addresses are generated, then the pieces of parallel pattern data (WA00 to WA80, WB00 to WB80), (WA01 to WA81, WB01 to WB81) . . . externally input on a time-shared basis are sequentially written in the burst addresses, and the memory itself controls the write inhibit and the write enable according to the pieces of mask data MA0 to MA7 and MD0 to MB7 input to the control pins.
The conventional pattern generator has no awareness of the burst address; hence, in the case of testing this kind of memory, the conventional pattern generator cannot generate, for each burst address, expectation data from mask data and pattern data written in the memory under test.
To facilitate a better understanding of the invention, a brief description will be given of a byte-wise masked test (a test conducted while in masking on the byte-wise basis) of the Direct Rambus DRAM.
In FIGS. 11 to 14 there shown operating states of the pattern generator and the Direct Rambus DRAM when the memory was written while masking on the byte-wise basis and read out.
FIG. 11 shows the operating states of the pattern generator and the memory under test at the time of initialization. The address generating part 13 (see FIG. 7) of the pattern generator 112 generates XB=#0 (see FIG. 11) as a start address, and the mask data generating part 14 outputs, as the mask data MD, xe2x80x9cFFFFxe2x80x9d whose bits are all xe2x80x9c1sxe2x80x9d in the FIG. 11 example.
Incidentally, the address XB and the mask data MD from the pattern generator 112 are output in parallel form, but in the waveform formatter 114 the address XB and the mask data MD in parallel form are converted by a pin select function of the formatter 114 to the packets COLC and COLM depicted in FIG. 9.
To the data I/O pins DQA0 to DQA8 and DQB0 to DQB8 of the memory under test 119 are sequentially input pieces of initialization data PDxc3x970 to PDxc3x977 of eight consecutive addresses. The initialization data PDxc3x970 corresponds to WA00 to WA80 and WB00 to WB80 depicted in FIGS. 8 and 9, and the data PDxc3x971 corresponds to WA01 to WA81 and WB01 to WB81. Similarly, the other remaining pieces of data PDxc3x972 to PDxc3x977 also correspond to the pieces of parallel pattern data DQA and DQB shown in FIGS. 8 and 9.
FIG. 11 shows how the initialization pattern is generated in the byte-wise masked test. Accordingly, control data such as the address XB and the mask data MD output from the pattern generator 112 is converted by the waveform formatter 112 to the packet signals COLC and COLM, thereafter being fed to the memory under test 119. The pieces of parallel pattern data PDxc3x970 to PDxc3x977 are also provided in tact via the multiplexer 17 to the waveform formatter 114 and converted to waveforms that meet the specifications of the memory under test 119 for input thereto.
FIG. 12 depicts the state of the memory 119 after the initialization shown in FIG. 11. Since the mask data MD=xe2x80x9cFFFFxe2x80x9d, a write is enabled for all bytes, and in the memory 119 pieces of data PDL0 o PDL7 and PDU0 to PDU7 are written as initialization data in the burst addresses, respectively.
In this case, PDL0 to PDL7 and PDU0 to PDU7 respectively correspond to the parallel data WA00 to WA87 and WB00 to WB87 depicted in FIGS. 9 and 10. That is, PDL0 corresponds to the data WA00 to WA80 of the low-order one byte of the address #0, and PDU0 corresponds to the data WB00 to WB80 of the high-order one byte of the address #0; the two-byte parallel pattern data of one address is shown as the low-order one-byte data and the high-order one-byte data.
FIG. 13 shows how to generate a byte-wise masked write pattern for the byte-wise masked test. In the byte-wise masking write, the pattern generator generates the start address XB=#0 and the parallel mask data MD. In the example of FIG. 13, data xe2x80x9cAA55xe2x80x9d (=1010101001010101) is set as the mask data MD. In this example, AA=101010110 is mask data for the low-order one byte of each of the burst addresses #0 to #7, and 55=01010101 is mask data for the high-order one byte of each of the burst addresses #0 to #7.
Parallel pattern data WDxc3x970 to WDxc3x977 is generated as a byte-wise masked write pattern for byte-wise masked test. As is the case with the parallel pattern data WDxc3x970 to Wdxc3x977 which forms the write pattern, the pieces of parallel pattern data are generated in the order WDxc3x970 (WA00 to WA80, WB00 to WB80), WDxc3x971 (WA01 to WA81, WB01 to WB81), . . . corresponding to the burst addresses #0 to #7, respectively. These pieces of parallel pattern data WDxc3x970, WDxc3x971, WDxc3x972, WDxc3x973, . . . , which form the write pattern, are provided intact as the signal DT to the memory under test.
The table of FIG. 14 shows stored contents of the memory under test after effecting the write therein while masking on the byte-wise basis. The mask data MA0 to MA7 on the first row in the table is mask data 55=01010101 for the low-order one byte of each of the addresses #0 to #7, and the mask data MB0 to MB7 on the second row is mask data AA=10101010 for the high-order one byte of each of the addresses #0 to #7. The one-byte parallel pattern data corresponding to the logic xe2x80x9c1xe2x80x9d bit of the mask data is write enabled. In this instance, at the DQA pin side (tile low-order one byte side) the pieces of the low-order one-byte data in the burst address #0, #2, #4 and #6 are changed to WDL0, WDL2, WDL4 and WDL6 written by the byte-wise masked write, while in the other burst addresses the initially written pieces of data PDL1, PDL3, PDL5 and PDL7 (see FIG. 12) are held unchanged. At the DQB pin side (the high-order one byte side), the pieces of high-order one-byte data in the burst addresses #1, #3, #5 and #7 are rewritten to WDU1, WDU3, WDU5 and WDU7, while in the other burst addresses the initially written pieces of data PDU0, PDU2, PDU4 and PDU6 are held unchanged.
As described above, when data written in the memory under test with memory cells masked on the byte-wise basis is read out of the memory and compared with the expectation data, the pieces of mask data MD (MA0 to MA7, MB0 to MB7) are provided in parallel signal form from the pattern generator 112 and are arranged irrespectively of the burst addresses; therefore, it is impossible, with the configuration of the pattern generator 112 shown in FIG. 5, to generate the expectation datas xe2x80x9cWDL0PDU0xe2x80x9d, xe2x80x9cPDL1WDU1xe2x80x9d, . . . ; xe2x80x9cPDL7WDU7xe2x80x9d in the FIG. 14 table from the parallel pattern data WDxc3x970 to WDxc3x977 and the parallel signal type mask data.
It is therefore an object of the present invention to provide a pattern generating method for use in testing such Direct Rambus DRAMs as mentioned above, a pattern generator utilizing the pattern generating method, and a memory tester using the pattern generator.
According to the present invention, there is provided a pattern generator for a memory tester which writes pattern data in a memory under test, then reads out thereof the written pattern data, and compares the read-out data with expectation data, the pattern generator comprising:
address generating means for generating a sequence of addresses to be applied to the memory under test;
pattern data generating means for generating parallel pattern data in which pieces of parallel data of plural bytes to be written, on a byte-wise basis, in memory cells of the memory under test specified by the addresses are arranged in time sequence in the order of burst addresses that are generated in the memory under test;
mask data generating means for generating parallel mask data which masks, on a byte-wise basis, plural-byte parallel data of the parallel pattern data generated by the pattern data generating means;
burst address generating means for generating, based on the address generated by the address generating means, burst addresses equivalent to burst addresses which are generated in the memory under test;
parallel-serial converting means for converting the parallel mask data from the mask data generating means to plural pieces of serial mask data in accordance with the burst addresses generated by the burst address generating means; and
expectation data generating means for deciding, based on the logic of each bit of the plural pieces of serial mask data, whether each byte of the plural-byte parallel data is write-enabled, and for generating, based on the decision result, parallel expectation data of plural bytes from the plural-byte parallel data and initialization data of the memory under test.
The memory tester according to the present invention comprises:
the pattern generator;
a waveform formatter supplied with parallel pattern data generated by the pattern generator on a byte-wise basis and parallel mask data, for supplying a memory under test with a test pattern signal of a waveform satisfying the specifications of the memory under test and a mask signal converted to a signal satisfying the specifications of the memory under test;
a logic comparator for making logic comparison between read-out data read out of the memory under test and expectation data generated by the expectation data generating part.
According to the present invention, there is provided a pattern generating method for a memory tester which writes pattern data in a memory under test, then reads out thereof the written pattern data, and compares the read-out data with expectation data, the pattern generating method comprising the steps of:
(a) initializing a burst type memory under test with initialization data;
(b) providing an address, pattern data and mask data to the memory under test to effect therein a byte-wise masked write of said pattern data;
(c) converting parallel mask data to plural pieces of serial mask data in accordance with burst addresses generated in a burst address generating part; and
(d) deciding, based on the logical value of each bit in each sequence of said serial mask data, whether data of each byte is write-enabled in a byte-wise masked write, and selecting, based on the decision result, either one of the initialization data and the byte-wise masked written pattern data on a byte-wise basis, thereby generating expectation data.
With the pattern generating method and the pattern generator of the present invention: burst addresses are generated at the pattern generator side; parallel mask data from the pattern generator is plural sequences of serial signals in accordance with the burst addresses; based on the logical value of each bit of the serial mask data, it is decided whether data of each byte is write-enabled in a byte-wise masked write; and, based on the decision result, either one of initialization data and the byte-wise masked written pattern data is selected on a byte-wise basis to thereby generate expectation data. Hence, correct expectation data can be generated with about the same configuration as in the past.